1. Field of the Invention
The present application generally relates to computer system memories and, more particularly, to very large dynamic RAM (DRAM) based cache memories which achieve set associative cache performance with the cost and complexity of a direct-mapped cache organization.
2. Background Description
N-way set associative caches are typically employed for improving the hit rate of cache memories. N-way set associative caches, where N>1, are complex, power hungry, and cost prohibitive compared to direct mapped caches, especially in very large caches constructed using DRAM for both the directory and data arrays. Therefore, a 1-way set associative cache organization, commonly referred to as a direct-mapped cache, is the preferred cache organization for very large caches built out of DRAM.
A problem with direct-mapped caches is their lower hit rate in comparison to set-associative caches, negatively impacting cache performance.